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1 f t n 1 6 c 8 2k x 8 nvsram nonvolatile s t atic ram fe a tures ? 25 n s, 3 5ns a n d 4 5 n s a cce s s t i m e s ? s t ore to n o nvo l at i l e e l emen t s i n itiated by hardware ? recall to sram in i tiat e d by h a r d w a re or power restore ? a u t o m a t i c s t ore t i m i n g ? 10ma t y p i c a l i cc at 2 00 n s cycle t i m e ? u n limi t ed read, w r i t e and recall cy c l es ? 1,00 0 ,0 0 0 s t ore cycles to n o n v olatile ele- men t s ? 10 0 - y e a r da t a rete n t i o n o ver f u ll in d u s t r i a l t e m p e r atu r e ra n g e ? co m mer c i a l a n d i n d u strial t e m p e r atu r es ? 28-pin 300 m i l p d i p , 3 0 0 mil soic and 350 mil soic pa c ka g es description t h e f or ce ft n 1 6 c 8 is a f a st s t atic ram with a n on- volatile element incorporated in each static memory cell. the sram can be read and written an unlimited number of times, while independent nonvolatile data resides in t he nonvolatile elements. data may easily be transferred from the sram to the nonvolatile ele- ments (the store operation), or from the nonvolatile elements to the sram (the recall operation), using the ne pin. transfers from the nonvolatile elements to the sram (the recall operation) also take place auto- matical l y on r e stor a t i on of pow e r . the ftn16c8 combines the high performanc e and ease of use of a fast sram with nonvolatile data integrity. t h e ftn16c8 f e atures i n dustry-s t an d ard p i no u t for nonvolatile ram s. block diagram column i/o column dec static ram array 32 x 512 row decoder input buffers 32 x 512 store/ recall control store recall a 7 a 8 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 g e w a 6 a 5 a 3 a 2 a 0 a 1 a 10 a 9 ne a 4 pin names a 0 - a 10 address inputs w write enable dq 0 - dq 7 data in/out e chip enable g output enable ne nonvolatile enable v cc power (+ 5v) v ss ground pin configurations ne nc a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dq 0 dq 1 dq 2 v ss v cc nc a 8 a 9 nc g w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a 10 e dq 7 dq 6 dq 5 dq 4 dq 3 28 - 300 pdip 28 - 300 soic 28 - 350 soic
ftn16c8 2 absolute maximum ratings a voltage on input relative to ground . . . . . . . . . . . . . .?0.5v to 7.0v voltage on input relative to v ss . . . . . . . . . . ?0.6v to (v cc + 0.5v) voltage on dq 0-7 . . . . . . . . . . . . . . . . . . . . . . ?0.5v to (v cc + 0.5v) temperature under bias . . . . . . . . . . . . . . . . . . . . . ?55 c to 125 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . ?65 c to 150 c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1w dc output current (1 output at a time, 1s duration) . . . . . . . . 15ma dc characteristics (v cc = 5.0v 10%) note b: i cc 1 and i cc 3 are dependent on output loading and cycle rate. the specified values are obtained with outputs unloaded. note c: i cc 2 is the average current required for the duration of the store cycle (t store ). note d: e v ih will not produce standby current levels until any nonvolatile cycle in progress has timed out. ac test conditions capacitance e (t a = 25 c, f = 1.0mhz) note e: these parameters are guaranteed but not tested. symbol parameter commercial industrial units notes min max min max i cc 1 b average v cc current 85 75 65 90 75 65 ma ma ma t avav = 25ns t avav = 35ns t avav = 45ns i cc 2 c average v cc current during store 3 3 ma all inputs don?t care, v cc = max i cc 3 b average v cc current at t avav = 200ns 5v, 25c, typical 10 10 ma w (v cc ? 0.2v) all others cycling, cmos levels i sb 1 d average v cc current (standby, cycling ttl input levels) 25 21 18 26 22 19 ma ma ma t avav = 25ns, e v ih t avav = 35ns, e v ih t avav = 45ns, e v ih i sb 2 d v cc standby current (standby, stable cmos input levels) 750 750 a e (v cc ? 0.2v) all others v in 0.2v or (v cc ? 0.2v) i ilk input leakage current 1 1 a v cc = max v in = v ss to v cc i olk off-state output leakage current 5 5 a v cc = max v in = v ss to v cc , e or g v ih v ih input logic ?1? voltage 2.2 v cc + .5 2.2 v cc + .5 v all inputs v il input logic ?0? voltage v ss ? .5 0.8 v ss ? .5 0.8 v all inputs v oh output logic ?1? voltage 2.4 2.4 v i out = ? 4ma v ol output logic ?0? voltage 0.4 0.4 v i out = 8ma t a operating temperature 0 70 ? 4 0 8 5 c input pulse levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to 3v input rise and fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns input and output timing reference levels . . . . . . . . . . . . . . . 1.5v output load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see figure 1 symbol parameter max units conditions c in input capacitance 8pf ? v = 0 to 3v c out output capacitance 7pf ? v = 0 to 3v figure 1: ac output loading 480 ohms 30 pf 255 ohms 5.0v including output scope and fixture note a: stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at condi- tions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect reliability.
ftn16c8 3 sram read cycles #1 & #2 (v cc = 5.0v 10%) note f: w must be high during sram read cycles and low during sram write cycles. ne must be high during entire cycle. note g: i/o state assumes e , g < v il , w > v ih , and ne v ih ; device is continuously selected. note h: measured + 200mv from steady state output voltage. sram read cycle #1: address controlled f, g sram read cycle #2: e controlled f no. symbols parameter ftn16c8 - 25 ftn16c8 - 35 ftn16c8 - 45 units # 1 , # 2 a l t. m i n m a x m i n m a x m i n m a x 1t elqv t acs chip enable access time 25 35 45 ns 2t avav f t rc read cycle time 25 35 45 ns 3t avqv g t aa address access time 25 35 45 ns 4t glqv t oe output enable to data valid 10 15 20 ns 5t axqx g t oh output hold after address change 5 5 5 ns 6t elqx t lz chip enable to output active 5 5 5 ns 7t ehqz h t hz chip disable to output inactive 10 13 15 ns 8t glqx t olz output enable to output active 0 0 0 ns 9t ghqz h t ohz output disable to output inactive 10 13 15 ns 10 t elicch e t pa chip enable to power active 0 0 0 ns 11 t ehiccl d, e t ps chip disable to power standby 25 35 45 ns data valid 5 t axqx 3 t avqv dq (data out) address 2 t avav 6 t elqx standby data valid 8 t glqx 4 t glqv dq (data out) e address 2 t avav g i cc active 1 t elqv 10 t elicch 11 t ehiccl 7 t ehqz 9 t ghqz
ftn16c8 4 sram write cycles #1 & #2 (v cc = 5.0v 10%) note i: if w is low when e goes low, the outputs remain in the high-impedance state. note j: e or w must be v ih during address transitions. ne v ih . sram write cycle #1 : w controlled j sram write cycle #2 : e controlled j no. symbols parameter ftn16c8 - 2 5 ftn16c8 - 35 ftn16c 8 - 4 5 units #1 #2 alt. minmaxminmaxminmax 12 t avav t avav t wc write cycle time 25 35 45 ns 13 t wlwh t wleh t wp write pulse width 20 25 30 ns 14 t elwh t eleh t cw chip enable to end of write 20 25 30 ns 15 t dvwh t dveh t dw data set-up to end of write 10 12 15 ns 16 t whdx t ehdx t dh data hold after end of write 0 0 0 ns 17 t avwh t aveh t aw address set-up to end of write 20 25 30 ns 18 t avwl t avel t as address set-up to start of write 0 0 0 ns 19 t whax t ehax t wr address hold after end of write 0 0 0 ns 20 t wlqz h, i t wz write enable to output disable 10 13 15 ns 21 t whqx t ow output active after end of write 5 5 5 ns previous data data out e address 12 t avav w 16 t whdx data in 19 t whax 13 t wlwh 18 t avwl 17 t avwh data valid 20 t wlqz 15 t dvwh high impedance 21 t whqx 14 t elwh data out e address 12 t avav w data in 13 t wleh 17 t aveh data valid high impedance 14 t eleh 18 t avel 19 t ehax 15 t dveh 16 t ehdx
ftn16c8 8 5 mode selection note k: an automatic recall takes place at power up, starting when v cc exceeds 4.25v and taking t restore . store cycles #1 & #2 (v cc = 5.0v 10%) note l: measured with w and ne both returned high, and g returned low. store cycles are inhibited below 4.0v. note m: once t wc has been satisfied by ne , g , w and e , the store cycle is completed automatically. any of ne , g , w or e may be used to terminate the store initiation cycle. note n: if e is low for any period of time in which w is high while g and ne are low, then a recall cycle may be initiated. store cycle #1: w controlled n store cycle #2: e controlled n e w g ne mode power hxxx not selected standby l h l h read sram active l l x h write sram active l h l l nonvolatile recall k active l l h l nonvolatile store i cc 2 l l l h l h l x no operation active no. symbols parameter min max units #1 #2 alt. 22 t wlqx l t elqx t store store cycle time 10 ms 23 t wlnh m t elnh t wc store initiation cycle time 20 ns 24 t ghnl output disable set-up to ne fall 0 ns 25 t ghel output disable set-up to e fall 0 ns 26 t nlwl t nlel ne set-up 0 ns 27 t elwl chip enable set-up 0 ns 28 t wlel write enable set-up 0 ns high impedance ne g w e dq (data out) 24 t ghnl 26 t nlwl 23 t wlnh 27 t elwl 22 t wlqx ne g w e dq (data out) high impedance 26 t nlel 25 t ghel 28 t wlel 23 t elnh 22 t elqx
ftn16c8 6 store inhibit/power-up recall (v cc = 5.0v + 10%) note o: t restore starts from the time v cc rises above v switch . store inhibit/power-up recall no. symbols parameter ftn16c8 units notes standard min max 29 t restore power-up recall duration 550 so 30 t store store cycle duration 10 ms 31 v switch low voltage trigger level 4.0 4.5 v 32 v reset low voltage reset level 3.6 v v cc v switch v reset power-up recall dq (data out) store inhibit 5v 29 t restore 31 32 power-up recall brown out store inhibit no recall (v cc did not go below v reset ) brown out store inhibit no recall (v cc did not go below v reset ) brown out store inhibit recall when v cc returns above v switch
ftn16c8 7 recall cycles #1, #2 & #3 (v cc = 5.0v 10%) note p: measured with w and ne both high, and g and e low. note q: once t nlnh has been satisfied by ne , g , w and e , the recall cycle is completed automatically. any of ne , g or e may be used to terminate the recall initiation cycle. note r: if w is low at any point in which both e and ne are low and g is high, then a store cycle will be initiated instead of a recall . recall cycle #1: ne controlled n recall cycle #2: e controlled n recall cycle #3: g controlled n, r no. symbols parameter min max units #1 #2 #3 33 t nlqx p t elqx t glqx recall cycle time 20 s 34 t nlnh q t elnh t glnh recall initiation cycle time 20 ns 35 t nlel t nlgl ne set-up 0 ns 36 t glnl t glel output enable set-up 0 ns 37 t whnl t whel t whgl write enable set-up 0 ns 38 t elnl t glel t elgl chip enable set-up 0 ns 39 t nlqz ne fall to outputs inactive 20 ns 40 t restore power-up recall duration 550 s ne g w e dq (data out) high impedance 34 t nlnh 36 t glnl 37 t whnl 38 t elnl 39 t nlqz 33 t nlqx ne g w e dq (data out) high impedance 35 t nlel 36 t glel 37 t whel 34 t elnh 33 t elqx ne g w e dq (data out) high impedance 35 t nlgl 33 t glqx 34 t glnh 37 t whgl 38 t elgl
ftn16c8 8 t h e ftn16c8 h a s two mo d e s of o perati o n: sram mode and nonvolatile mode, determined by the state of the ne pin. when in sram mode, the mem- ory operates as a standard fast static ram . while in nonvolatile mode, data is transferred in parallel from sram to nonvolatile elements or from nonvolatile elements to sram . noise considerations note that the ftn16c 8 is a hi g h -spe e d memory and so must have a high-frequency bypass capaci- tor of approximately 0.1 f connected between v cc and v ss , using leads and traces that are as short as possible. as with all high-speed cmos ics, normal careful routing of power, ground and signals will help prevent noise problems. sram read t h e ftn16c8 p erf o r ms a read cyc l e w h en e v e r e and g are low and ne and w are high. the address specified on pins a 0-10 determines which of the 2,048 data bytes will be accessed. when the read is initi- ated by an address transition, the outputs will be valid after a delay of t avqv ( read cycle #1). if the read is initiated by e or g , the outputs will be valid at t elqv or at t glqv , whichever is later ( read cycle #2). the data outputs will repeatedly respond to address changes within the t avqv access time without the need for transitions on any control input pins, and will remain valid until another address change or until e or g is brought high or w or ne is brought low. sram write a write cycle is performed whenever e and w are low and ne is high. the address inputs must be sta- ble prior to entering the write cycle and must remain stable until either e or w goes high at the end of the cycle. the data on pins dq 0-7 will be writ- ten into the memory if it is valid t dvwh before the end of a w controlled write or t dveh before the end of an e controlled write . it is recommended that g be kept high during the entire write cycle to avoid data bus contention on the common i/o lines. if g is left low, internal circuitry will turn off the output buffers t wlqz after w goes low. nonvolatile store a store cycle is performed when ne , e and w and low and g is high. while any sequence that achieves this state will initiate a store , only w initi- ation ( store cycle #1) and e initiation ( store cycle #2) are practical without risking an unintentional sram write that would disturb sram data. during a store cycle, previous nonvolatile data is erased and the sram contents are then programmed into nonvolatile elements. once a store cycle is initi- ated, further input and outp ut are disabled and the dq 0-7 pins are tri-stated until the cycle is complete. if e and g are low and w and ne are high at the end of the cycle, a read will be performed and the out- puts will go active, signaling the end of the store . nonvolatile recall a recall cycle is performed when e , g and ne are low and w is high. like the store cycle, recall is initiated when the last of the four clock signals goes to the recall state. once initiated, the recall cycle will take t nlqx to complete, during which all inputs are ignored. when the recall completes, any read or write state on the input pins will take effect. internally, recall is a two-step procedure. first, the sram data is cleared, and second, the nonvolatile information is transferred into the sram cells. the recall operation in no way alters the data in the nonvolatile cells. the nonvolatile data can be recalled an unlimited number of times. as with the store cycle, a transition must occur on any one control pin to cause a recall , preventing inadvertent multi-triggering. on power up, once v cc exceeds 4.25v, a recall cycle is automatically initi- ated. due to this automatic recall , sram operation cannot commence until t restore after v cc exceeds 4.25v. power-up recall during power up, or after any low-power condition (v cc < 3.0v), an internal recall request will be latched. when v cc once again exceeds 4.25v, a recall cycle will automatically be initiated and will take t restore to complete. device operation
ftn16c8 9 if the ftn16c8 is in a write s t a t e at the end of power-up recall , the sram data will be corrupted. to help avoid this situation, a 10k ohm resistor should be connected either between w and system v cc or between e and system v cc . hardware protect t h e ftn16c 8 o f f e rs t w o l e v e l s of p r o t ec t i on to suppress inadvertent store cycles. if the control signals (e , g , w and ne ) remain in the store con- dition at the end of a store cycle, a second store cycle will not be started. the store (or recall ) will be initiated only after a transition on any one of these signals to the required state. in addition to multi-trigger protection, store s are inhibited when v cc is below 4.0v, protecting against inadvertent store s. low average active power t h e ftn16c8 dra w s si g nificantly less current when it is cycled at times longer than 55ns. figure 2 shows the relationship between i cc and read cycle time. worst-case current consumption is shown for both cmos and ttl input levels (commercial tem- perature range, v cc = 5.5v, 100% duty cycle on chip enable). figure 3 shows the same relationship for write cycles. if the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. the overall average current drawn by t h e ftn16c8 de p en d s on the fol l owi n g it e m s: 1) cmos vs. ttl input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of read s to write s; 5) the operating temperature; 6) the v cc level; and 7) i/o loading. figure 2: i cc (max) reads 0 20 40 60 80 100 50 100 150 200 cycle time (ns) ttl cmos average active current (ma) figure 3: i cc (max) writes 0 20 40 60 80 100 50 100 150 200 cycle time (ns) ttl cmos average active current (ma)
ftn16c 8 10 ordering information temperature range blank = commercial (0 to 70c) i = industrial (?40 to 85c ) access time 25 = 25ns 35 = 35ns 45 = 45ns lead finish blank = 85%sn/15%pb f = 100% sn (matte tin) package p = plastic 28-pin 300 mil dip n = plastic 28-pin 300 mil soic s = plastic 28-pin 350 mil soic - p f 45 i ftn16c8
ftn16c8 1 1 all trademarks acknowledged ashley crt, henley, marlborough, wilts, sn8 3rh tel: +44(0)1264 731200 fax:+44(0)1264 731444 e - mail info@forcetechnologies.co.uk tech@forcetechnologies.co.uk sales@forcetechnologies.co.uk www.forcetechnologies.co.uk unless otherwise stated in this scd, force technologies ltd reserve t he right to make changes, without notice, in the products, including circuits, cells and/or software, described or contained herein in order to improve design and/or performance. force technologies resumes no responsibility or liability for the use of any of these products, conveys no licence or any title under patent, copyright, or mask work to these products, and makes no representation or warranties that that these products are free from patent, copyright or mask work infringement, unless otherwise speci fied. life support applications force technologies products are not designed for use in life support appliances, devices or systems where malfunction of a fo rc e technologies product can reasonably be expected to result in a personal injury. force technologies customers using or se ll in g fo rce technologies products for use in such applications do so at their own risk and agree to fully indemnify force te ch no lo gi es resulting from such improper use or sale. copyright force technologies ltd 2003

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